Electronic design automation (EDA) systems provide software tools in which electronic circuit designs can be described, simulated, and translated by machine into a design realization. A conventional mechanism for describing a circuit design is hardware description language (HDL). A user defines a behavioral description of a design using HDL and the HDL design is processed to generate a physical implementation. HDL design tools include HDL simulation environments, such as the MODELSIM environment from the Model Technology Company, and implementation environments, such as SYNPLIFY from Synplicity, Inc. Another type of circuit design system, referred to as a high level modeling system (HLMS), provides a higher level of abstraction for describing and simulating an electronic circuit than does an HDL simulation environment or implementation environment. An HLMS generally provides a mathematical representation of signals as compared to standard logic vectors in HDL. The Xilinx SYSTEM GENERATOR TOOL FOR DSP from Xilinx, Inc. and the SIMULINK and MATLAB environments from MathWorks, Inc. are exemplary high level modeling systems.
A design implemented in an HLMS can be simulated using software algorithms that model the hardware behavior of the blocks that comprise the model. Sometimes it is beneficial to use hardware, in addition to software, during a simulation. Using hardware in the simulation loop can accelerate simulation speeds dramatically, while also providing real-time hardware verification capabilities. The process of breaking a design into pieces and simulating those pieces using subsidiary design tools is referred to as “co-simulation.” When the subsidiary tool of interest is a reconfigurable hardware platform, the process is referred to as “hardware co-simulation.” In hardware co-simulation, the simulation of a portion of a design under test (DUT) is offloaded to hardware, while the other portion of the DUT continues to be simulated on the host PC through software models. The DUT can include the hardware being modeled (“hardware model”), and hardware co-simulation logic for providing a co-simulation interface to the hardware model. The host simulation environment (software) passes stimuli to the input ports of the DUT running on hardware via a communication interface. Similarly, the communication interface captures results from the output ports of the DUT and then read back to the host simulation environment.
Conventionally, an HLMS has often been used to design and simulate systems that are easily expressed as data flow diagrams (e.g., digital filters). As HLMS's mature, designers are seeking to incorporate larger systems into an HLMS, such as video-processing engines (e.g., MPEG encoders and decoders) and system-on-chip (SoC) designs, for example. Such designs may include instances of embedded instruction processors that communicate with custom logic peripherals
A processor-based system designed in an HLMS can be modeled in hardware and simulated using hardware co-simulation. When the processor-based system is configured as a DUT, the hardware co-simulation logic can drive the processor-based system with a single clock. However, the single clock wiring scheme has some limitations in practical designs. Notably, the instruction processor may expect a specific input clock frequency that is not available from the hardware co-simulation logic. For example, the hardware co-simulation logic may be capable of providing specific frequencies (e.g., 33.33 MHz, 50 MHz, 66.67 MHz, and 100 MHz). However, the instruction processor (and other associated logic) may require an input clock frequency of 125 MHz, which cannot be provided by the hardware co-simulation logic. In other cases, the processor-based system is required to run with a clock frequency different from that of the custom logic developed using the HMLS. These different clock frequency requirements cannot be provided through single clock wiring. Moreover, in some DUTs, both the instruction processor and the hardware co-simulation logic may include digital clock management (DCM) components. In such case, single clock wiring results in cascaded DCM components, which may introduce undesired clock jitters and prevent the design portion simulated in the hardware to meet specific timing requirements.
Accordingly, there exists a need in the art for a method and apparatus for modeling processor-based circuit models that overcome the aforementioned deficiencies associated with single clock wiring.